Avalanche photo diode detectors (APD) are utilized in a wide range of applications including low level light detection, laser rangefinders, LIDAR, photon counting, optical tomography, fluorescence detection, particle sizing and counting, and communication systems. The APD is particularly useful in fiber optic based network communication systems, specifically in long-reach/high sensitivity optical receivers.
Typically, the ADP is reverse biased, during operation, by a relatively high voltage. When illuminated with photons of the proper wavelength, the diode undergoes avalanche breakdown creating a large signal current. The ratio between the current flowing with no illumination (the “dark” current) and the signal current flowing during photon induced avalanche breakdown is the APD gain, typically referred to as a dimensionless constant knows as a multiplication factor (M).
FIG. 1 is a circuit diagram of a typical APD fixed bias voltage controller 100. FIG. 2 is a graph 200 of the multiplication factor M as a function of bias voltage. Plot 202 indicates that M increases as bias voltage increases. Many circuits of the prior art, such as the circuit illustrated in FIG. 1, are designed to bias the APD at a fixed voltage Vtarget, to achieve a high operating gain at a multiplication factor Mopt. This maximizes light sensitivity so that even weak optical signals can be detected reliably.
With reference to FIGS. 1 and 2, a D.C. voltage source 106 feeds a voltage regulator 102 which supplies the bias voltage to APD 116. Typically voltage regulator 102 boosts the voltage levels of D.C. source 106, as many APDs require high voltages (30-100V) which are not commonly available in monolithic IC systems. Current flowing through the APD 116 (Iapd) is monitored by current mirror 104, which produces a scaled current output (Iapd/k) that is fed to the current input of analog to digital converter (ADC) 112. Voltage drop across current mirror 104 is assumed to be negligible when compared to the bias voltage Vbias. Signal current Iapd also flows into trans-impedance amplifier (TIA) 118 to convert the signal current to output signal voltages.
Resistor RL 114 is placed in series with APD 116 to limit current at high illumination levels. A voltage divider consisting of resistors 120 and 122 (Rd1, Rd2) provides a scaled voltage Vfb on a line 124, which is proportional to Vbias, which is fed to analog controller 108, where it is compared to the desired fixed bias voltage setpoint 126 (Vtarget) input to the system. A digital error correction output 128 (Vctrl) from analog controller 108 is input to voltage regulator 102 to correct any deviations in Vbias.
The digital output 130 of A/D converter 112, which represents the value of Iapd, is sent to circuit module 110, which estimates the level of the incoming optical power level Prx. This can be accomplished by using the formula Prx=Iapd/(M*Ro), where M is the multiplication factor and Ro is the responsivity. Iapd is measured via current mirror 104, and M can be estimated from graph 200 since the voltage drop across RL (=Iapd*RL) is also known. Ro can be estimated as a function of wavelength and/or other variables.
While the APD fixed bias voltage controller 100 of FIG. 1 has the potential advantage of simplicity, it suffers from a number of important disadvantages. For example, a disadvantage of the APD fixed bias voltage controller 100 is the need for a series resistor 114 (RL) to limit the current through the APD at high input optical power levels Prx.
FIG. 3 is a graph 300 of Optical Power versus M factor and system power consumption for the circuit of FIG. 1. A plot 304 illustrates the impact of input optical power, plotted as the log(Prx) in a dB scale, on the M factor. At very low optical power levels, Iapd remains low and the voltage drop of Iapd through RL is small compared to Vbias (which is fixed by regulator 102). As optical power Prx increases, Iapd increases due to increasing avalanche current and the voltage drop across RL increases. This reduces the effective bias voltage across the APD, lowering the M factor. At relatively low Prx levels, it is more desirable to keep the M factor at its optimum level, to reduce bit error rates that can occur as M factor (and bias voltage) is dropped. However, with the fixed series resistor (RL) 114, the drop in M factor with increasing Prx is unavoidable.
Another disadvantage of 100 of FIG. 1 is power consumption. As seen in FIG. 3, a plot 302 illustrates the approximate trend in power consumption as Prx is increased. The output voltage from regulator 102 is held fixed held fixed independent of the Iapd current level. Since the electrical power that must be delivered is at least Vbias×Iapd, not taking into account efficiencies in regulator 102, significant increases in Iapd will result in significant increases in power consumed by the circuit of FIG. 1. Power dissipation is increasingly critical in communication systems with high port densities or battery backed up communication systems.
A further disadvantage of APD fixed bias voltage controller 100 is that, at high Prx levels, the M factor must be maintained at a low value to limit the signal current through the APD. Given the functioning mechanism of the circuit of FIG. 1, the actual M factor is determined by the voltage output by regulator 102 and the voltage drop across RL 114, both of which determine the actual bias voltage across APD 116. The M factor may not be precisely controlled in that it is subject to many variables including the specific characteristics of the APD as well as circuit tolerances of RL and other components. The variability in the M factor can result in significant increases in the bit error rates which are not desirable.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.